Bias generation circuit, buffer circuit including the bias generation circuit and semiconductor system including the buffer circuit

ABSTRACT

A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.

CROSS-REFERENCES TO RELATED APPLICATION

The present application is a divisional application of U.S. patentapplication Ser. No. 17/073,066, filed on Oct. 16, 2020, and claimspriority under 35 U.S.C. § 119(a) to Korean application number10-2020-0068164, filed on Jun. 5, 2020, in the Korean IntellectualProperty Office, which is incorporated herein by reference in itsentirety.

BACKGROUND 1. Technical Field

Various embodiments may generally relate to a semiconductor device, moreparticularly to a bias generation circuit, a buffer circuit includingthe bias generation circuit and a semiconductor system including thebuffer circuit.

2. Related Art

A semiconductor device may include a plurality of buffer circuitsconfigured to input/output various signals such as data, clock signals,etc.

Operations of the buffer circuit may be affected by the power voltageand the frequency.

For example, when a level of the power voltage is higher than a targetlevel, the delay time of an output signal from the buffer circuit may bedecreased. In contrast, when the level of the power voltage is lowerthan the target level, the delay time of the output signal from thebuffer circuit may be increased.

SUMMARY

In example embodiments of the present disclosure, a bias generationcircuit may include a bias generator and compensator. The bias generatormay be configured to generate a bias voltage based on a referencevoltage. The compensator may be configured to detect level changes of apower voltage. The compensator may be configured to control a level ofthe bias voltage based on detection results.

In example embodiments of the present disclosure, a bias generationcircuit may include a comparison circuit, a voltage generation circuit,a voltage change tracker and a bias level controller. The comparisoncircuit may be configured to compare a feedback voltage with a referencevoltage and configured to output comparison results. The voltagegeneration circuit may be configured to generate a bias voltage througha first current path and a second current path. The feedback voltage maybe generated through the first current path based on the output of thecomparison circuit. The second current path may be generated bymirroring a current flowing through the first current path. The voltagechange tracker may be configured to detect a change of a power voltage.The bias level controller may be configured to control a level of thebias voltage based on an output of the voltage change tracker.

In example embodiments of the present disclosure, a buffer circuit mayinclude a current mode circuit and a bias generation circuit. Thecurrent mode circuit may be configured to generate an output signalbased on a power voltage and an input signal. The current mode circuitmay be configured to compensate for a transition timing change of theoutput signal based on a level of a bias voltage. The bias generationcircuit may be configured to generate the bias voltage based on areference voltage. The bias generation circuit may be configured todetect level changes of the power voltage. The bias generation circuitmay be configured to control the level of the bias voltage based ondetection results.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and another aspects, features and advantages of the subjectmatter of the present disclosure will be more clearly understood fromthe following detailed description taken in conjunction with theaccompanying drawings, in which:

FIG. 1 is a view, illustrating a buffer circuit of a semiconductordevice based on example embodiments;

FIG. 2 is a view, illustrating a current mode circuit in FIG. 1;

FIG. 3 is a view, illustrating a bias generation circuit in FIG. 1; and

FIG. 4 is a view, illustrating a semiconductor system with a buffercircuit based on example embodiments.

DETAILED DESCRIPTION

Various embodiments of the present invention will be described ingreater detail with reference to the accompanying drawings. The drawingsare schematic illustrations of various embodiments (and intermediatestructures). As such, variations from the configurations and shapes ofthe illustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected, Thus, the described embodimentsshould not be construed as being limited to the particularconfigurations and shapes illustrated herein but may include deviationsin configurations and shapes which do not depart from the spirit andscope of the present invention as defined in the appended claims.

The present invention is described herein with reference tocross-section and/or plan illustrations of idealized embodiments of thepresent invention. However, embodiments of the present invention shouldnot be construed as limiting the inventive concept. Although a fewembodiments of the present invention will be shown and described, itwill be appreciated by those of ordinary skill in the art that changesmay be made in these embodiments without departing from the principlesand spirit of the present invention.

In the following description of the embodiments, when a parameter isreferred to as being “predetermined”, it may be intended to mean that avalue of the parameter is determined in advance when the parameter isused in a process or an algorithm. The value of the parameter may be setwhen the process or the algorithm starts or may be set during a periodthat the process or the algorithm is executed.

It will be understood that although the terms “first”, “second”, “third”etc, are used herein to describe various elements, these elements shouldnot be limited by these terms. These terms are only used to distinguishone element from another element, Thus, a first element in someembodiments could be termed a second element in other embodimentswithout departing from the teachings of the present disclosure.

Further, it will be understood that when an element is referred to asbeing “connected” or “coupled” to another dement, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an dement is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present.

Example embodiments provide a bias generation circuit that may becapable of compensating a change of signal delay time based on a powervoltage.

Example embodiments also provide a buffer circuit with theabove-mentioned bias generation circuit.

Example embodiments still also provide a semiconductor system with theabove-mentioned buffer circuit.

FIG. 1 is a view, illustrating a buffer circuit of a semiconductordevice based on example embodiments.

Referring to FIG. 1, a buffer circuit 100 of a semiconductor devicebased on example embodiments may include a current mode circuit 200 anda bias generation circuit 400.

The current mode circuit 200 may be configured to generate a pluralityof output signals OUT and OUTB based on a power voltage VDD, a biasvoltage CMLBIAS, a plurality of input signals IN/INB, and a first enablesignal EN1.

The power voltage VDD may correspond to a voltage that is applied to apower terminal. The power voltage VDD may be an external voltage or aninternal voltage.

Hereinafter, the power voltage VDD may be applied to the power terminal.

The external voltage may include a voltage applied from an externaldevice of the buffer circuit 100 or the semiconductor device with thebuffer circuit 100, The internal voltage may include a voltage that isgenerated in the semiconductor device by using the external voltage.

The input signals IN/INB and the output signals OUT and OUTB may includedifferential signals.

The current mode circuit 200 may be activated based on the first enablesignal EN1.

The bias generation circuit 400 may be configured to generate the biasvoltage CMLBIAS based on a reference voltage VREF, the first enablesignals EN1 and EN1B, and a second enable signals EN2 and EN2B.

The first enable signals EN1 and EN1B may be activated or inactivatedbased on various operational conditions, for example, whether the buffercircuit 100 is required to be operated or not. The first enable signalsEN1 and EN1B may be provided from the semiconductor device with thebuffer circuit 100 or the external device.

The second enable signals EN2 and EN2B may be activated or inactivatedbased on various operational conditions, for example, a random timing atwhich the bias voltage CMLBIAS may be controlled, a power-up operationof the semiconductor device, etc. The second enable signals EN2 and EN2Bmay be provided from the semiconductor device with the buffer circuit100 or an external device.

The bias generation circuit 400 may be configured to generate the biasvoltage CMLBIAS based on the reference voltage VREF. The bias generationcircuit 400 may be configured to control a level of the bias voltageCMLBIAS based on the level changes of the power voltage.

When the first enable signals EN1 and EN1B are activated, the biasgeneration circuit 400 may perform an operation to generate the biasvoltage CMLBIAS.

When the second enable signals EN2 and EN2B are activated, the biasgeneration circuit 400 may perform an operation to control the level ofthe bias voltage CMLBIAS based on the level changes of the powervoltage.

FIG. 2 is a view, illustrating a current mode circuit in FIG. 1.

Referring to FIG. 2, the current mode circuit 200 may include a firstresistor 210, a second resistor 211, a first transistor 212, a secondtransistor 213, and a current sink circuit 214 and 215.

The first resistor 210 may be connected to a power terminal.

The second resistor 211 may be connected to the power terminal parallelywith the first resistor 210.

A source terminal of the first transistor 212 may be connected to thefirst resistor 210, Any of the input signals IN/IN B, for example, theinput signal INB, may be inputted into a gate terminal of the firsttransistor 212.

Any one of the output signals OUT and OUTB, for example, the outputsignal OUT, may be outputted from a node to which the first resistor 210and the source terminal of the first transistor 212 may be connected.

A source terminal of the second transistor 213 may be connected to thesecond resistor 211. Any of the input signals IN/INB, for example, theinput signal IN, may be inputted into a gate terminal of the secondtransistor 213.

Any one of the output signals OUT and OUTB, for example, the outputsignal OUTB, may be outputted from a node to which the second resistor211 and the source terminal of the second transistor 213 may beconnected.

One end of the current sink circuit 214 and 215 may be commonlyconnected to the drain terminals of the first and second transistors 212and 213. The other end of the current sink circuit 214 and 215 may beconnected to the ground terminals of the first and second transistors214 and 215.

The current sink circuit 214 and 215 may include a third transistor 214and a fourth transistor 215.

A source terminal of the third transistor 214 may be commonly connectedto the drain terminals of the first and second transistors 212 and 213,A gate terminal of the third transistor 214 may receive the first enablesignal EN1.

A source terminal of the fourth transistor 215 may be connected to adrain terminal of the third transistor 214, A drain terminal of thefourth transistor 215 may be connected to the ground terminal. A gateterminal of the fourth transistor 215 may receive the bias voltageCMLBIAS.

Alternatively, the gate terminal of the third transistor 214 may receivethe bias voltage CMLBIAS. The gate terminal of the fourth transistor 215may receive the first enable signal EN1.

When the first enable signal EN1 is at a high level, the current modecircuit 200 may increase or decrease a sink current based on the levelof the bias voltage CMLBIAS to compensate for the transition timingchanges of the output signals OUT and OUTB.

For example, when the level of the power voltage VDD is lower than atarget level, the transition timings of the output signals OUT and OUTBmay be delayed compared to the target timing.

The level of the bias voltage CMLBIAS may be inversely proportional tothe level changes of the power voltage VDD. That is, when the level ofthe power voltage VDD is increased, the level of the bias voltageCMLBIAS may be decreased. In contrast, when the level of the powervoltage VDD is decreased, the level of the bias voltage CMLBIAS may beincreased.

Thus, when the level of the power voltage VDD is lower than the targetlevel, the level of the bias voltage CMLBIAS may be increased. As aresult, the sink current may also be increased by the level of the biasvoltage CMLBIAS increasing so that the transition timings of the outputsignals OUT and OUTB may be quickened.

As mentioned above, the transition timings of the output signals OUT andOUTB, which may be delayed by the level of the power voltage VDDdecreasing, may be quickened to compensate for the transition timingchanges of the output signal OUT and OUTB.

FIG. 3 is a view, illustrating a bias generation circuit in FIG. 1.

Referring to FIG. 3, the bias generation circuit 400 may include a biasgenerator 500 and a compensator 600.

The bias generator 500 may be configured to generate the bias voltageCMLBIAS based on the first enable signals EN1 and EN1B and the referencevoltage VREF.

The reference voltage VREF may have a characteristic that isproportional to an absolute temperature. That is, when the temperaturerises, the level of the reference voltage VREF may also be increased. Incontrast, when the temperature drops, the level of the reference voltageVREF may also be decreased.

The bias generator 500 may include a comparison circuit 510 and avoltage generation circuit 520.

When the first enable signal EN1 is at a predetermined level, forexample, a high level, the comparison circuit 510 may compare a feedbackvoltage VFBK with the reference voltage VREF to output comparisonresults.

The comparison circuit 510 may include first to sixth transistors511˜516, a resistor 517, and a capacitor 518.

A source terminal of the first transistor 511 may be connected to thepower terminal. A drain terminal of the first transistor 511 may beconnected to a first node N1.

A drain terminal of the second transistor 512 may be connected to thefirst node N1.

A source terminal of the third transistor 513 may be connected to thepower terminal. A drain terminal of the third transistor 513 may becommonly connected to a gate terminal of the first transistor 511 and agate terminal of the third transistor 513.

A drain terminal of the fourth transistor 514 may be connected to thedrain terminal of the third transistor 513. A gate terminal of thefourth transistor 514 may receive the feedback voltage VFBK.

A drain terminal of the fifth transistor 515 may be commonly connectedto a source terminal of the second transistor 512 and a source terminalof the fourth transistor 514. A gate terminal of the fifth transistor515 may receive the first enable signal EN1.

A drain terminal of the sixth transistor 516 may be connected to asource terminal of the fifth transistor 515. A source terminal of thesixth transistor 516 may be connected to the ground terminal.

The reference voltage VREF may be applied to one end of the resistor517, The other end of the resistor 517 may be commonly connected to agate terminal of the second transistor 512 and a gate terminal of thesixth transistor 516.

One end of the capacitor 518 may be commonly connected to the other endof the resistor 517, the gate terminal of the second transistor 512, andthe gate terminal of the sixth transistor 516, The other end of thecapacitor 518 may be connected to the ground terminal.

Alternatively, the capacitor 518 may be excluded from the comparisoncircuit 510.

When the capacitor 518 is excluded from the comparison circuit 510, thereference voltage VREF may be directly applied to the gate terminal ofthe second transistor 512 and the gate terminal of the sixth transistor516.

The comparison circuit 510 may compare the feedback voltage VFBK withthe reference voltage VREF to output the comparison results through thefirst node N1.

Because the reference voltage VREF may have the temperature proportioncharacteristic, the voltage that is outputted from the first node N1 mayhave a level having a compensated temperature level.

When the first enable signal EN1B is a predetermined level, for example,a low level, the voltage generation circuit 520 may generate the biasvoltage CMLBIAS based on the output from the comparison circuit 510,i.e., the voltage level of the first node N1.

The voltage generation circuit 520 may include first to fifthtransistors 521˜525 and a resistor 526.

A source terminal of the first transistor 521 may be connected to thepower terminal, A gate terminal of the first transistor 521 may receivethe voltage of the first node N1.

A source terminal of the second transistor 522 may be connected to adrain terminal of the first transistor 521. A gate terminal of thesecond transistor 522 may be connected to the ground terminal. A drainterminal of the second transistor 522 may be connected to a second nodeN2.

A source terminal of the third transistor 523 may be connected to thepower terminal. A gate terminal of the third transistor 523 may receivethe voltage of the first node N1.

A source terminal of the fourth transistor 524 may be connected to adrain terminal of the third transistor 523, A gate terminal of thefourth transistor 524 may receive the first enable signal EN1B, A drainterminal of the fourth transistor 524 may be connected to a third nodeN3.

A drain terminal and a gate terminal of the fifth transistor 525 may becommonly connected to the third node N3. A source terminal of the fifthtransistor 525 may be connected to the ground terminal.

One end of the resistor 526 may be connected to the second node N2. Theother end of the resistor 526 may be connected to the ground terminal.

A voltage that is applied to the second node N2 may be provided to thecomparison circuit 510 as the feedback voltage VFBK.

A voltage that is applied to the third node N3 may be outputted as thebias voltage CMLBIAS.

The voltage generation circuit 420 may include a current mirror. Thecurrent mirror may include first current paths 521, 522, and 526 andsecond current paths 523, 524, and 525. The second paths 523, 524, and525 may be formed by mirroring the first current path 521, 522, and 526.

The current amount of the first current paths 521, 522, and 526 may becontrolled based on the voltage of the first node N1. The bias voltageCMLBIAS may be generated by the second current paths 523, 524, and 525that are configured to mirror the current amount of the first currentpaths 521, 522, and 526.

The first current paths 521, 522, and 526 may provide the comparisoncircuit 510 with the voltage of the second node N2 that corresponds tothe bias voltage CMLBIAS as the feedback voltage VFBK.

The compensator 600 may be configured to detect the level changes of thepower voltage. The compensator 600 may be configured to control thelevel of the bias voltage CMLBIAS based on detection results.

The compensator 600 may be configured to detect low-frequency changesthat are formed by removing high-frequency noises from the level of thepower voltage. The compensator 600 may be configured to control thelevel of the bias voltage CMLBIAS based on detection results.

The compensator 600 may include a voltage change tracker 610, a low passfilter 620, and a bias level controller 630.

The voltage change tracker 610 may be configured to detect the change ofthe power voltage VDD.

The voltage change tracker 610 may include first to fifth transistors611˜615.

A source terminal of the first transistor 611 may be connected to thepower terminal. A gate terminal of the first transistor 611 may receivethe second enable signal EN2. A drain terminal of the first transistor611 may be connected to a fourth node N4.

A drain terminal of the second transistor 612 may be connected to thefourth node N4. A gate terminal of the second transistor 612 may receivethe second enable signal EN2.

A drain terminal of the third transistor 613 may be connected to asource terminal of the second transistor 612, A source terminal of thethird transistor 613 may be connected to the ground terminal.

A source terminal of the fourth transistor 614 may be connected to thepower terminal. A gate terminal of the fourth transistor 614 may receivethe second enable signal EN2.

A gate terminal of the fifth transistor 615 may be connected to a gateterminal of the fourth transistor 614. A drain terminal of the fifthtransistor 615 may be connected to the gate terminal of the fifthtransistor 615, A source terminal of the fifth transistor 615 may beconnected to the ground terminal.

When the second enable signal EN2 is at a predetermined level, forexample, a high level the voltage change tracker 610 may change thevoltage level of the fourth node N4 based on the level changes of thepower voltage VDD to detect the level changes of the power voltage VDD.

The low pass filter 620 may be configured to remove high-frequencycomponents from the detection results of the power voltage level throughthe voltage change tracker 610, Thus, only low-frequency components maypass through the low pass filter 620.

The low pass filter 620 may include a capacitor 621 and a resistor 622.

The capacitor 621 may be connected between a fifth node N5 and theground terminal.

The resistor 622 may be connected between the fourth node N4 and thefifth node N5.

The bias level controller 630 may be configured to control the level ofthe bias voltage CMLBIAS based on the outputs of the low pass filter 620and the second enable signals EN2 and TN_ENB.

The bias level controller 630 may include first to fourth transistors631˜634.

The current path with the first to fourth transistors 631˜634 may bereferred to as a third current path.

A source terminal of the first transistor 631 may be connected to thepower terminal. A gate terminal of the first transistor 631 may receivethe voltage of the first node N1. A drain terminal of the firsttransistor 631 may be connected to the gate terminal of the firsttransistor 631.

A source terminal of the second transistor 632 may be connected to thedrain terminal of the first transistor 631, A gate terminal of thesecond transistor 632 may receive the second enable signal EN2B. A drainterminal of the second transistor 632 may be connected to a sixth nodeN6.

A drain terminal of the third transistor 633 may be connected to thesixth node N6. A gate terminal of the third transistor 633 may beconnected to the fifth node N5.

A drain terminal of the fourth transistor 634 may be connected to asource terminal of the third transistor 633. A gate terminal of thefourth transistor 634 may receive the second enable signal EN2. A sourceterminal of the fourth transistor 634 may be connected to the groundterminal.

Hereinafter, the operations of the bias generation circuit 400 may beillustrated in detail.

When the first enable signals EN1 and EN1B are activated, for example,EN1=H and EN1B=L, the bias generator 500 may generate the bias voltageCMLBIAS with a level in which the temperature change may be compensatedbased on the reference voltage VREF.

When the second enable signals EN2 and EN2B are activated, for example,EN2=H and EN2B=L, the compensator 600 may detect the change of the powervoltage VDD to compensate for the level of the bias voltage CMLBIAS thatcorresponds to the detection results.

For example, when the level of the power voltage VDD is increased, thevoltage level of the fourth node N4 may be proportionally increased to aresistor ratio between the first transistor 611 and the second and thirdtransistors 612 and 613 in the voltage change tracker 610.

The high-frequency component in the voltage level change of the fourthnode N4 may be removed by the low pass filter 620. Only thelow-frequency component may be applied to the bias level controller 630through the fifth node N5.

The current flowing through the second current paths 523, 524, and 525may be formed by mirroring the current flowing through the first currentpaths 521, 522, and 526.

A first current I1 that flows through the second current paths 523, 524,and 525 and a second current I2 that flows through the third currentpaths 631, 632, and 634 may have the same current source as the firstnode N1. Thus, the first current I1 and the second current I2 may beconstant and the same regardless of the change of the power voltage VDD.

The relationship between the first to fourth currents (I1+I2=I3+I4) maybe established by the conservation law of the electrical charge.

When a current amount (I1 and I2) is constant, the fourth current I4 maybe increased by increasing the voltage level of the fourth node N4 sothat the third current I3 may be decreased.

The level of the bias voltage CMLBIAS may be proportionally decreased tothe decreasing of the third current I3.

In contrast, when the level of the power voltage VDD is decreased, thevoltage level of the fourth node N4 may be proportionally decreased tothe resistor ratio between the first transistor 611 and the second andthird transistors 612 and 613 in the voltage change tracker 610.

The high-frequency component in the voltage level change of the fourthnode N4 may be removed by the low pass filter 620. Only thelow-frequency component may be applied to the bias level controller 630through the fifth node N5.

When the current amount (I1 and I2) is constant, the fourth current I4may be decreased by decreasing the voltage level of the fourth node N4so that the third current I3 may be increased.

The level of the bias voltage CMLBIAS may be proportionally increased tothe increasing of the third current I3.

Therefore, the bias voltage CMLBIAS may have the level that iscompensated based on the temperature change and the level change of thepower voltage VDD.

As mentioned above, the bias voltage CMLBIAS may have the level that iscompensated based on the level change of the power voltage VDD as wellas the temperature change. Particularly, the level of the bias voltageCMLBIAS may be compensated based on the change caused by removing thehigh-frequency component among the level change of the power voltageVDD.

Thus, the current mode circuit 200 may have a uniform transition timingof the output signals OUT and OUTB, regardless of the change of thepower voltage VDD and the noises.

FIG. 4 is a view, illustrating a semiconductor system with a buffercircuit based on example embodiments.

Referring to FIG. 4, a semiconductor system 1000 with the buffer circuitof example embodiments may include a semiconductor memory 1100 and amemory controller 1200.

The semiconductor memory 1100 may include a first pad 1101, a second pad1104, a clock buffer 1102, a distribution circuit 1103, a transmitter TX1105, and a receiver RX 1106.

An external dock signal WCK, provided from the memory controller 1200,may be inputted into the clock buffer 1102 through the first pad 1101.

The distribution circuit 1103 may be configured to distribute an outputof the dock buffer 1102 to the transmitter 1105 and the receiver 1106.

The transmitter 1105 may be configured to transmit internal data to thememory controller 1200 through the second pad 1104 based on an output ofthe distribution circuit 1103.

The receiver 1106 may be configured to receive data DQ that is inputtedthrough the second pad 1104 based on the output of the distributioncircuit 1103.

The memory controller 1200 may include a first pad 1201, a second pad1203, a clock buffer 1202, and a data buffer 1204.

The memory controller 1200 may output an internal clock signal as theexternal clock signal WCK through the clock buffer 1202 and the firstpad 1201.

The data DQ that is received through the second pad 1203 may be providedto an internal circuit through the data buffer 1204.

The buffer circuit 100 of example embodiments may be used for the clockbuffer 1102, the clock buffer 1202, and the data buffer 1204.

The dock buffer 1102, the clock buffer 1202, and the data buffer 1204may have uniform transition timings of output signals that are generatedby buffering the clock signal or the data based on the bias voltageregardless of the temperature change, the change of the power voltageand the noises.

Therefore, because the transition timings of the clock buffer 1102, theclock buffer 1202, and the data buffer 1204 may be uniformly maintainedregardless of the change of the power voltage, operational timingmargins of the semiconductor memory 1100 and the memory controller 1200may be ensured to improve operational reliability of the semiconductormemory 1100 and the memory controller 1200.

The above described embodiments of the present invention are intended toillustrate and not to limit the present invention, Various alternativesand equivalents are possible. The invention is not limited by theembodiments described herein. Nor is the invention limited to anyspecific type of semiconductor device. Another additions, subtractions,or modifications are obvious in view of the present disclosure and areintended to fall within the scope of the appended claims.

What is claimed is:
 1. A buffer circuit comprising: a current modecircuit configured to generate an output signal based on a power voltageand an input signal and configured to compensate for a transition timingchange of the output signal based on a level of a bias voltage; and abias generation circuit configured to generate the bias voltage based ona reference voltage, configured to detect a level change of the powervoltage, and configured to control the level of the bias voltage basedon detection results.
 2. The buffer circuit of claim 1, wherein the biasgeneration circuit is configured to remove a high-frequency componentfrom the level change of the power voltage and configured to detect alow-frequency component in the level change of the power voltage.
 3. Thebuffer circuit of claim 1, wherein the bias generation circuitcomprises: a bias generator configured to generate the bias voltagebased on a reference voltage; and a compensator configured to detect thelevel change of the power voltage and configured to control the level ofthe bias voltage based on the detection results.
 4. The buffer circuitof claim 3, wherein the reference voltage has a temperature proportioncharacteristic.
 5. The buffer circuit of claim 3, wherein the biasgenerator comprises: a comparison circuit configured to compare afeedback voltage with the reference voltage and to output comparisonresults; and a voltage generation circuit configured to generate a biasvoltage through a first current path and a second current path based onthe output of the comparison circuit, the first current path configuredto generate the feedback voltage, and the second current path formed bymirroring a current flowing through the first current path.
 6. Thebuffer circuit of claim 3, wherein the compensator is configured todetect a low-frequency change in the level of the power voltage andconfigured to control the level of the bias voltage based on thedetection results.
 7. The buffer circuit of claim 3, wherein thecompensator comprises: a voltage change tracker configured to detect thechange of the power voltage; a low pass filter configured to remove ahigh-frequency component from an output of the voltage change tracker toallow a low-frequency component to pass through the low pass filter; anda bias level controller configured to control the level of the biasvoltage based on an output of the low pass filter.
 8. The buffer circuitof claim 3, wherein the bias generator is activated by a first enablesignal, and wherein the compensator is activated by a second enablesignal.